CMOS device typically have an output stage that includes a PMOS transistor and NMOS transistor coupled in series between two power sources. The transistor drains are coupled together to an output pad and, depending upon the device configuration, the transistor gates are either coupled to an output of another CMOS device (e.g., a driver) or to a power source. Typical device configurations include inverters, and various buffers.
Because of their thin oxides and high impedances, CMOS devices are very susceptible to damage from electrostatic discharge ("EDS"), especially before they are mounted in a circuit board. Electrostatic potentials are easily generated. For example, a person can accumulate static charge simply by walking across a room, or by wearing nylon. If the person then handles a CMOS device, the accumulated charge can discharge through the device, causing ESD damage.
After being mounted in a circuit board, CMOS devices are somewhat protected from ESD damage by the circuit board layout, and various protective devices provided at the board input/output connections. However before such mounting, CMOS devices are "bare" and are especially vulnerable to ESD damage. While bare, the output NMOS and PMOS transistors are off because no power source is coupled to the CMOS device.
It is known in the art how to protect the input pad of a bare CMOS device from ESD using diodes, resistors or transistors. However it is not known how to protect a bare CMOS device from ESD at the output pad. Design constraints do not permit coupling a protective resistor or diode in series with the output pad to provide output pad ESD protection. Although negative potential ESD at the output pad will not harm the CMOS device, a positive potential ESD can destroy the device's output NMOS transistor. Fortunately, the output PMOS transistor needs no output pad ESD protection because it is a buried channel device, and is therefore relatively "robust".
A positive potential ESD at the output pad causes the turned-off NMOS transistor to enter a "snapback" mode. In this mode, drain current increases uncontrollably and is dissipated across a small, localized channel area. The resulting current density in this area quickly becomes excessive, and localized breakdown occurs, destroying the NMOS transistor.
It is therefore an object of the present invention to protect the output NMOS transistor of a CMOS device from a positive ESD voltage at the output pad, without significantly degrading device performance, and without significantly increasing manufacturing cost. Further, the ESD protection should be effective even when the CMOS device is unconnected to other devices.